1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor chip capable of implementing wire bonding over active circuits (also referred to as “BOAC”).
2. Description of the Prior Art
Accompanying progress of the semiconductor technology, critical dimensions of integrated circuits are continually shrunk. Therefore, bonding pads which spread around on a chip are obstacles for reducing the chip size. For this reason, implementing wire bonding over active circuits is a trend for chips design and manufacturing.
FIG. 1 is a schematic cross-sectional diagram of a BOAC integrated circuit structure according to the prior art. As shown in FIG. 1, a BOAC integrated circuit structure 10 of the prior art has a plurality of active circuits on a semiconductor substrate 12. The plurality of active circuits include input/output (I/O) devices/circuits or electrostatic discharge (ESD) devices/circuits, and are made up of metal-oxide-semiconductor field-effect transistors (MOSFET) 14, 16, and 18, shallow trench isolations (STI) 20 and 22, ion diffusion regions 24, 26, 28, and 30, an inter-layer dielectric (ILD) 32, inter-metal dielectrics (IMD) 34, 36 and 38, and interconnection metal layers 40, 42, 44, 46, 48, 50, and 52. A portion of the surface of the top interconnection metal layer 52 is covered by a barrier layer 54, a protection layer 56, and a bondable metal pad 58.
According to FIG. 1, in the BOAC integrated circuit structure 10 of the prior art, the top interconnection metal layer 52 is set over the covering region of the bondable metal pad 58 and electrically links with lower active circuits formed underneath through an outside wire. Therefore, mechanical stresses press on the bondable metal pad 58 directly during bonding, and bonds between the bondable metal pad 58, the barrier layer 54, and the top interconnection metal layer 52 and the lower integrated circuits are destroyed. Moreover, the outside wire, which is formed for electrically linking the top interconnection metal layer 52 and the lower active circuits, is unfavorable for chip size shrinkage.